Parity flag

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In computer programming, the parity flag is a processor flag which indicates if the numbers of set bits is odd or even in the binary representation of the result of the last operation. It is normally a single bit in a processor status register.

For example, assume a machine where a set parity flag indicates even parity. If the result of the last operation were 26 (11010 in binary), the parity flag would be 0 since the number of set bits is odd. Similarly, if the result were 10 (1010 in binary) then the parity flag would be 1.

Some microcontrollers, notably the ubiquitous 8051, include a parity flag to help with implementing RS-232 and other serial communication protocols, in lieu of a UART with parity support.

x86 processors

x86 processors include a parity flag because they are descended (via the Intel 8086, 8080 and 8008) from the Datapoint 2200 terminal, which was designed for serial communication duties.

In x86 processors, the parity flag reflects the parity of only the least significant byte of the result, and is set if the number of set bits is even. This is an odd parity bit: the total number of set bits in the byte result, plus the parity flag, is odd. According to the Intel 80386 manual, the parity flag is changed in the x86 processor family by the following instructions:

  • All arithmetic instructions (ADD, ADC, SUB, SBB, INC, DEC, NEG, XADD, AAD, AAM, DAA, DAS), except ADOC and ADOX;
  • Compare (CMP) and string compare (SCAS) instructions, equivalent to a subtract instruction without storing the result;
  • Logical instructions (XOR, AND, OR) except NOT;
  • the TEST instruction (equivalent to the AND instruction without storing the result);
  • The shift instructions (SAL, SAR, SHL, SHR. SHLD, SHRD), but not rotates (ROL, ROR, RCL, RCR);
  • The direct-to-FLAGS floating-point comparisons, where the parity flag is set to indicate an unordered result: x87 comparisons FCOMI, FCOMIP, FUCOMI and FUCOMIP, and SSE1 comparisons COMISD, COMISS, UCOMISD, UCOMISS; and
  • Instructions which write to the entire flags register: POPF, SAHF, IRET, interrupts, or any other instruction which causes a hardware task switch.

More exoteric arithmetic instructions set the parity flag to an undefined value: multiply (MUL, IMUL), divide (DIV, IDIV), ASCII adjust after addition/subtraction (AAA, AAS).

Logical instructions which leave the parity flag undefined are bit test (BT, BTC, BTR, BTS), bit scan (BSF, BSR, LZCNT), and the BMI instructions which affect flags (ANDN, BEXTR, BLSI, BLSMSK, BLSR, BZHI, TZCNT). The POPCNT instruction and the SSE4.1 instructions TEST and PTEST clear the parity flag unconditionally.

The parity flag is tested by conditional jump instructions; the JP instruction jumps to the given target when the parity flag is set and the JNP instruction jumps if it is not set. The flag determines the result of the relevant conditional set (SETP, SETNP) and conditional move (CMOVP, CMOVNP, FCMOVU, FCMOVNU) instructions. (The "P" and "NP" conditions may also be written "PE" and "PO", respectively.) The flag may be also read directly with instructions such as LAHF or PUSHF, which copy the flags register to the AH register or the stack, respectively.

One common reason to test the parity flag is to check an unrelated x87-FPU flag. The FPU has four condition flags (C0 to C3), but they can not be tested directly, and instead need to first be copied to the flags register with the sequence FSTSW AX; SAHF. When this happens, C0 is placed in the carry flag, C2 in the parity flag and C3 in the zero flag.[1] The C2 flag is set when e.g. incomparable floating point values (NaN or unsupported format) are compared with the FUCOM instructions. The 80486 added the FCOMI instructions which send the comparison results directly to the x86 flags, using the same convention.

The Windows debugging engine for x86-64 had a bug where it reported the parity flag as the opposite of what it actually is for over 20 years, which was fixed in 2026.[2]

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